Differential amplifiers are commonly used in the read data buffers or write data buffers of memory devices, such as dynamic random access memories ("DRAMs"). Write data buffers couple write data from one or more data terminals of the memory device to a memory array during a memory write operation. Read data buffers couple read data from the memory array to one or more data terminals of the memory device during a memory read operation. Typically, data are coupled to and from the memory array in complimentary form, and are coupled to and from the data terminals in single ended form. Thus, write and read data coupled between the data terminals and the memory array must be converted between single-ended and complimentary data formats.
The logic level corresponding to the single-ended data is generally determined by whether the voltage of the single-ended data signal is greater or less than respective high and low threshold voltages. The logic level corresponding to the complimentary data is generally determined by whether the voltage of the data signal is greater than or less than the voltage of the complimentary data signal. If the voltage of the data signal is greater than the voltage of the complimentary data signal, the data is considered to be a logic "1". If the voltage of the data signal is less than the voltage of the complimentary data signal, the data is considered to be a logic "0".
The respective voltages corresponding to the complimentary data coupled to and from the array often differ only slightly from each other. As a result, is can be difficult to determine whether the voltage of the data signal is greater than the voltage of the complimentary data signal (corresponding to logic "1") or the voltage of the data signal is less than the voltage of the complimentary data signal (corresponding to logic "0"). This problem is exacerbated in the presence of noise or other interference that may be coupled to the data and complimentary data lines.
In a differential amplifier, noise is usually impressed on both the data signal line and its complementary data signal line. Since the differential amplifier responds to differences in the voltage applied between its differential inputs, it does not significantly respond to noise signals applied to both inputs. Thus, a potential advantage of using a differential amplifier to amplify the complimentary data signals is that it will often be insensitive to noise. Thus, differential amplifiers display a high degree of immunity to common mode signals such as noise.
Ideally, differential amplifiers utilize symmetry to produce equal currents and voltages in identical portions of the differential amplifier circuitry. One conventional differential amplifier 10 is shown in FIG. 1. The amplifier 10 includes a pair of NMOS transistors 12, 14 having their sources coupled to each other and to a current sink 16. As is known in the art, the current sink 16 draws a predetermined constant current from the transistors 12, 14. The gates of the transistors 12, 14 receive respective differential input signals +V.sub.IN and -V.sub.IN. at respective input terminals 20, 22. The drains of the transistors 12, 14 are coupled to a supply voltage V.sub.CC through respective load resistors 26, 28. An output voltage V.sub.O is developed between output terminals 30, 32 corresponding to the voltage difference between the input signals +V.sub.IN less -V.sub.IN.
In operation, when the magnitude of +V.sub.IN increases and the magnitude of -V.sub.IN decreases, the percentage of the current I conducted by the transistor 12 increases and the percentage of the current I conducted by the transistor 14 decreases, although the sum of the current flowing through the two transistors 12, 14 remains essentially constant. As a result, the voltage drop across the resistor 26 increases and the voltage drop across the resistor 28 decreases. The increased voltage drop across the resistor 26 causes the voltage at the output terminal 30 to decrease while the decreased voltage drop across the resistor 28 causes the voltage at the output terminal 32 to increase. Typically, the change in voltage of the output voltage V.sub.O between the terminals is significantly greater than the change in voltage of +V.sub.IN less -V.sub.IN. The amplifier 10 responds in the opposite manner to a decrease in the magnitude of +V.sub.IN and an increase in the magnitude of -V.sub.IN.
While the differential amplifier 10 does perform adequately in many applications, it has a variety of shortcomings when used in more demanding applications. For this reason, an improved differential amplifier 40 shown in FIG. 2 was developed. The differential amplifier 40 is the result of adding to the differential amplifier 10 of FIG. 1 PMOS transistors 46, 48 used as load impedances, a PMOS transistor 50 used as a current source, and an NMOS transistor 52 used as a current sink.
In operation, an increase in the input voltage +V.sub.IN increases the channel resistance of the PMOS transistor 46 and decreases the channel resistance of the NMOS transistor 12. As a result, the voltage on the output terminal 30 decreases. At the same time, the corresponding increase in the input voltage -V.sub.IN decreases the channel resistance of the PMOS transistor 48 and increases the channel resistance of the NMOS transistor 14. As a result, the voltage on the output terminal 32 increases.
When transistors 50, 52 are used to control the sum of the current through the transistors 12, 14, it can be difficult to bias the transistors 50, 52 in a stable manner. As a result, internal bias is often used. The internal bias of the differential amplifier 40 of FIG. 2 results from the connection of the output terminal 30 to the gates of the current source and sink transistors 50, 52, respectively. As the voltage on the output terminal 30 increases, the channel resistance of the NMOS current sink transistor 52 decreases, but the channel resistance of the PMOS current source transistor 50 increases. Conversely, as the voltage on the output terminal 30 decreases, the channel resistance of the NMOS current sink transistor 52 increases and the channel resistance of the PMOS current source transistor 50 decreases. As a result, the sum of the current through the transistors 12, 14 remains essentially constant.
Although the differential amplifier 40 shown in FIG. 2 is biased in a stable manner, the manner in which the biasing circuitry is connected can cause other problems. These problems result from the fact that the differential amplifier 40 is not entirely symmetrical because the bias circuit is connected to only one output terminal, namely the output terminal 30. There is no corresponding connection of a bias circuit to the output terminal 32. As a result, the bias circuit loads the PMOS transistor 46 and the NMOS transistor 12 generating the output voltage on the output terminal 30, but there is no corresponding load on the PMOS transistor 48 and the NMOS transistor 14 generating the output voltage on the output terminal 32. This lack of symmetry can result in offset voltages at the differential output terminals 30, 32 as well as a reduced ability to reject common mode voltages, such as noise.
As mentioned above, differential amplifiers are commonly used in memory devices to couple data signals between a memory array and data terminals of the memory device. For such applications, it is important that the differential amplifier be able to operate at a high speed since the demand for higher performance in computers and computing circuitry requires memories that will transfer data at a faster rate. It is therefore important that any solution to the above described problem does not limit the operating speed of differential amplifiers. For example, noise in differential amplifiers could be reduced by low-pass filtering to limit the bandwidth of differential amplifiers, but doing so would limit the speed at which differential amplifiers could transfer data.
There is therefore a need for a high speed, inherently symmetrical differential amplifier that can be biased in a stable manner.